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low cost, low power, differential adc driver data sheet ad8137 rev. e information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infring ements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and register ed trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2004 C 2012 analog devices, inc. all rights reserved. features fully differential extremely low power with power - down feature 2.6 ma quiescent supply current @ 5 v 450 a in power - down mode @ 5 v high speed 110 mhz large signal 3 db bandwidth @ g = 1 450 v/s slew rate 12- bit sfdr performance @ 500 khz fast s ettling time: 100 ns to 0.02% low input offset voltage: 2 .6 mv max low input offset current: 0.45 a max differential input and output differential - to - differential or single - ended - to - differential operation rail - to - rail output adjustable output common - mode voltage externally adjustable gain wide supply voltage range: 2.7 v to 12 v available in small soic package qualified for automotive applications applications adc drivers automotive vision and safety systems automotive infotainment systems portable instru mentation battery - powered applications single - ended - to - differential converters differential active filters video amplifiers level shifters functional block dia gram 04771-0-001 ?in 1 v ocm 2 v s+ 3 +out 4 +in 8 pd 7 v s? 6 ?out 5 ad8137 figure 1 . r g = 1k? v o, dm = 0.1v p-p frequency (mhz) normalized closed-loop gain (db) 3 2 1 0 ?12 ?11 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0.1 1 10 100 1000 04771-0-002 g = 5 g = 10 g = 1 g = 2 figure 2 . small signal res ponse for various gains general descripton the ad8137 is a low cost differential driver with a rail - to - rail outp ut that is ideal for driving adcs in systems that are sensitive to power and cost. the ad8137 is easy to apply, and its internal common - mode feedback architecture allows its output common - mode voltage to be controlled by the voltage applied to one pin. the internal feedback loop also provides inherently b alanced ou tputs as well as suppression of even - order harmonic distortion products. fully differential and single - ended - to - differential gain configurations are easily realized by the ad8137 . external feedback ne tworks consisting of four resistor s determine the closed - loop gain of the amplifier . the power - down feature is beneficial in critical low power applications. the ad8137 is manufactured on analog devices , inc., proprietary second - generation xfcb process, enabling it to achieve high levels of performance with very low power consumption. the ad8137 is available in the small 8 - lead soic package and 3 mm 3 mm lfcsp pack age . it is rated to operate over the extended industrial temperature range of ? 40c to +125c.
ad8137* product page quick links last content update: 11/01/2016 comparable parts view a parametric search of comparable parts evaluation kits ? ad-fmcmotcon2-ebz evaluation board ? universal evaluation board for single differential amplifiers documentation application notes ? an-0990: terminating a differential amplifier in single- ended input applications ? an-0992: active filter evaluation board for differential amplifiers ? an-1026: high speed differential adc driver design considerations ? an-1363: meeting biasing requirements of externally biased rf/microwave amplifiers with active bias controllers ? an-282: fundamentals of sampled data systems ? an-584: using the ad813x differential amplifier ? an-649: using the analog devices active filter design tool data sheet ? ad8137:??low cost, low power, differential adc driver data sheet user guides ? ug-474: evaluation board for differential amplifiers offered in 8-lead soic packages tools and simulations ? adi diffampcalc? ? ad8137 spice macro-model reference materials product selection guide ? high speed amplifiers selection table tutorials ? mt-075: differential drivers for high speed adcs overview ? mt-076: differential driver analysis ? mt-218: multiple feedback band-pass design example design resources ? ad8137 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all ad8137 engineerzone discussions sample and buy visit the product page to see pricing options technical support submit a technical question or find your regional support number * this page was dynamically generated by analog devices, inc. and inserted into this data sheet. note: dynamic changes to the content on this page does not constitute a change to the revision number of the product data sheet. this content may be frequently modified.
ad8137 data sheet rev. e | page 2 of 32 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functi onal block diagram .............................................................. 1 general descripton .......................................................................... 1 revision history ............................................................................... 2 spe cifications ..................................................................................... 3 absolute maximum ratings ............................................................ 9 thermal resistance ...................................................................... 9 ma ximum power dissipation ..................................................... 9 esd caution .................................................................................. 9 pin configuration and function descriptions ........................... 10 typical performance characteristics ........................................... 11 test circuits ..................................................................................... 21 theory of operation ...................................................................... 22 applications information .............................................................. 23 analyzing a typical application with matched r f and r g networks ...................................................................................... 23 estimating noise, gain, and bandwith with matched feedback networks .................................................................... 23 driving an adc with greater than 12 - bit performance ...... 27 outline dimensions ....................................................................... 29 ordering guide .......................................................................... 30 automotive products ................................................................. 30 revision history 7/1 2 rev. d to rev. e changes to features section and applications section ............... 1 added ad8137w ............................................................... universal updated outline dimensions ....................................................... 28 changes to ordering guide .......................................................... 29 added automotive products section .......................................... 29 7/ 10 rev. c to rev. d changes to p ower - down section, added figure 6 8, renumbered subsequent figures ................................................. 24 changes to ordering guide .......................................................... 27 12/09 rev. b to rev. c changes to product title, applications section, and general description section .......................................................................... 1 changes to input resistance parameter unit, table 3 ................. 5 added epad mnemonic/description , table 6 ............................ 7 added figure 61; renumbered sequentially .............................. 17 moved test circuits section .......................................................... 18 changes to power down section ................................................. 2 4 updated outline dimensions ....................................................... 2 6 7/05 rev. a to rev. b changes to ordering guide .......................................................... 24 8/04 rev. 0 to rev. a. added 8 - lead lfcsp ......................................................... universal c hanges to layout .............................................................. universal changes to product title and figure 1 ........................................... 1 changes to specifications ................................................................. 3 changes to absolute maximum ratings ........................................ 6 changes to figure 4 and figure 5 .................................................... 7 added figure 6, figure 20, figure 23, figure 35, figure 48, and figure 58; renumbered s e quentially ...................................... 7 changes to figure 32 ...................................................................... 12 changes to figure 40 ...................................................................... 13 changes to figure 55 ...................................................................... 16 changes to table 7 and figure 63 ................................................. 18 changes to equation 19 ................................................................. 19 changes to figure 64 and figure 65 ............................................. 20 changes to figure 66 ...................................................................... 22 added driving an adc with greater than 12 - bit performance section ...................................................................... 22 changes to ordering guide .......................................................... 24 updated outline dimensions ....................................................... 24 5/04 revision 0: initial version
data sheet ad8137 rev. e | page 3 of 32 specifications v s = 5 v, v ocm = 0 v (@ 25c, differential gain = 1, r l, dm = r f = r g = 1 k?, unless otherwise noted, t min to t max = ?40 c to +125c). table 1. parameter conditions min typ max unit differential input performance dynamic performance ?3 db small signal bandwidth v o, dm = 0.1 v p -p 64 76 mhz ad8137w only: t min -t max 63 mhz ?3 db larg e signal bandwidth v o, dm = 2 v p -p 79 110 mhz ad8137w only: t min -t max 79 mhz slew rate v o, dm = 2 v step 450 v/s settling time to 0.02% v o, dm = 3.5 v step 100 n s overdrive recovery time g = 2, v i, dm = 12 v p - p triangle wave 85 n s noise/ harmonic performance sfdr v o, dm = 2 v p - p, f c = 500 khz 90 db v o, dm = 2 v p - p, f c = 2 mhz 76 db input voltage noise f = 50 khz to 1 mhz 8.25 nv/hz input current noise f = 50 khz to 1 mhz 1 pa/hz dc performance input offset voltage v ip = v in = v ocm = 0 v ?2.6 0.7 +2.6 mv ad8137w only: t min -t max ?5.0 +5.0 mv input offset voltage drift t min to t max 3 v/c input bias current t min to t max 0.5 1.0 a input offset current 0.1 0.45 a ad8137w only: t min -t max 0.45 a open - loop gain 91 db input characteristics input common - mode voltage range ?4 +4 v ad8137w only: t min -t max ?4 +4 v input resistance different ial 800 k? common - mode 400 k? input capacitance common - mode 1.8 pf cmrr v icm = 1 v 66 79 db ad8137w only: t min -t max 66 db output characteristics output voltage swing each single - ended output, r l, dm = 1 k? v s? + 0.55 v s+ ? 0.55 v ad8137w only: t min -t max v s? + 0.55 v s+ ? 0.55 v output current 20 ma output balance error f = 1 mhz ?64 db v ocm to v o, cm performance v ocm dynamic performance ?3 db bandwidth v o, cm = 0.1 v p -p 58 mhz slew rate v o, cm = 0.5 v p -p 63 v/s gain 0.992 1.000 1.008 v/v ad8137w only: t min -t max 0.990 1.008 v/v v ocm input characteristics input voltage range ?4 +4 v ad8137w only: t min -t max ?4 +4 v input resistance 35 k? input offset voltage ?28 11 +28 mv ad8137w only: t min - t max ?28 +28 mv input voltage noise f = 100 khz to 1 mhz 18 nv/hz
ad8137 data sheet rev. e | page 4 of 32 parameter conditions min typ max unit input bias current 0.3 1.1 a ad8137w only: t min -t max 1.1 a cmrr v o, dm /v ocm , v ocm = 0.5 v 62 75 db ad8137w only: t min -t max 62 db power supply operat ing range +2.7 6 v ad8137w only: t min -t max +2.7 6 v quiescent current 3.2 3.60 ma ad8137w only: t min -t max 3.65 ma quiescent current, disabled power - down = low 750 900 a ad8137w only: t min - t max 900 a psrr v s = 1 v 79 91 db ad8137 w only: t min -t max 79 db pd pin threshold voltage v s? + 0.7 v s? + 1.7 v ad8137w only: t min -t max v s? + 0.7 v s? + 1.7 v input current power - down = high/low 150/210 170/240 a ad8137w only: t min -t max 180/245 a opera ting temperature range ?40 +125 c
data sheet ad8137 rev. e | page 5 of 32 v s = 5 v, v ocm = 2.5 v (@ 25c, differential gain = 1, r l, dm = r f = r g = 1 k?, unless otherwise noted, t min to t max = ? 40 c to +125c). table 2. parameter conditions min typ max unit differe ntial input performance dynamic performance ?3 db small signal bandwidth v o, dm = 0.1 v p -p 63 75 mhz ad8137w only: t min - t max 61 mhz ?3 db large signal bandwidth v o, dm = 2 v p -p 76 107 mhz ad8137w only: t min -t max 76 mhz slew rate v o, dm = 2 v step 375 v/s settling time to 0.02% v o, dm = 3.5 v step 110 ns overdrive recovery time g = 2, v i, dm = 7 v p - p triangle wave 90 ns noise/harmonic performance sfdr v o, dm = 2 v p - p, f c = 500 khz 89 db v o, dm = 2 v p - p, f c = 2 mhz 73 db input voltage noise f = 50 khz to 1 mhz 8.25 nv/hz input current noise f = 50 khz to 1 mhz 1 pa/hz dc performance input offset voltage v ip = v in = v ocm = 0 v ?2.7 0.7 +2.7 mv ad8137w only: t min -t max ?5.0 +5.0 mv input offset voltage drift t min to t max 3 v/c input bias current t min to t max 0.5 0.9 a input offset current 0.1 0.45 a ad8137w only: t min -t max 0.45 a open - loop gain 89 db input characteristics input common - mode voltage range 1 4 v ad8137w only: t min -t max 1 4 v input resistance differential 80 0 k ? common - mode 400 k ? input capacitance common - mode 1.8 pf cmrr v icm = 1 v 64 90 db ad8137w only: t min -t max 64 db output characteristics output voltage swing each single - ended output, r l, dm = 1 k? v s? + 0.45 v s+ ? 0.45 v ad8137w on ly: t min -t max v s? + 0.45 v s+ ? 0.45 v output current 20 ma output balance error f = 1 mhz ?64 db v ocm to v o, cm performance v ocm dynamic performance ?3 db bandwidth v o, cm = 0.1 v p -p 60 mhz slew rate v o, cm = 0.5 v p -p 61 v/s g ain 0.980 1.000 1.020 v/v ad8137w only: t min -t max 0.975 1.020 v/v v ocm input characteristics input voltage range 1 4 v ad8137w only: t min -t max 1 4 v input resistance 35 k? input offset voltage ?25 7.5 +25 mv ad8137w only: t min -t max ?25 +25 mv
ad8137 data sheet rev. e | page 6 of 32 parameter conditions min typ max unit input voltage noise f = 100 khz to 5 mhz 18 nv/hz input bias current 0.25 0.9 a ad8137w only: t min -t max 0.9 a cmrr v o, dm /v ocm , v ocm = 0.5 v 62 75 db ad8137w only: t min - t max 62 db power supply operating range +2 .7 6 v ad8137w only: t min -t max +2.7 6 v quiescent current 2.6 2.8 ma ad8137w only: t min -t max 2.8 ma quiescent current, disabled power - down = low 450 600 a ad8137w only: t min -t max 600 a psrr v s = 1 v 79 91 db ad8137w only: t min -t m ax 79 db pd pin threshold voltage v s? + 0.7 v s? + 1.5 v ad8137w only: t min -t max v s? + 0.7 v s? + 1.5 v input current power - down = high/low 50/110 60/120 a ad8137w only: t min -t max 60/125 a operating temperature r ange ?40 +125 c
data sheet ad8137 rev. e | page 7 of 32 v s = 3 v, v ocm = 1.5 v (@ 25c, differential gain = 1, r l, dm = r f = r g = 1 k?, unless otherwise noted, t min to t max = ? 40 c to +125c). table 3. parameter conditions min typ max unit differential input perfor mance dynamic performance ?3 db small signal bandwidth v o, dm = 0.1 v p -p 61 73 mhz ad8137w only: t min - t max 58 mhz ?3 db large signal bandwidth v o, dm = 2 v p -p 62 93 mhz ad8137w only: t min -t max 62 mhz slew rate v o, dm = 2 v s tep 340 v/s settling time to 0.02% v o, dm = 3.5 v s tep 110 n s overdrive recovery time g = 2, v i, dm = 5 v p -p triangle wave 100 n s noise/harmonic performance sfdr v o, dm = 2 v p - p, f c = 500 khz 89 db v o, dm = 2 v p - p, f c = 2 mhz 71 db inpu t voltage noise f = 50 khz to 1 mhz 8.25 nv/hz input current noise f = 50 khz to 1 mhz 1 pa/hz dc performance input offset voltage v ip = v in = v ocm = 0 v ?2.75 0.7 +2.75 mv ad8137w only: t min -t max ?5.2 5 +5.25 mv input offset voltage drift t min to t max 3 v/c input bias curren t t min to t max 0.5 0.9 a input offset current 0.1 0.4 a ad8137w only: t min - t max 0.4 a open - loop gain 87 db input characteristics input common - mode voltage range 1 2 v ad8137w only: t min -t max 1 2 v input resistance differential 800 k ? common - mode 400 k ? input capacitance common - mode 1.8 pf cmrr v icm = 1 v 64 80 db ad8137w only: t min -t max 64 db output characteristics output voltage swing each single - ended output, r l, dm = 1 k? v s? + 0.37 v s+ ? 0.37 v ad8137w on ly: t min -t max v s? + 0.37 v s+ ? 0.37 v output current 20 ma output balance error f = 1 mhz ?64 db v ocm to v o, cm performance v ocm dynamic performance ?3 db bandwidth v o, cm = 0.1 v p -p 61 mhz slew rate v o, cm = 0.5 v p -p 59 v/s g ain 0.96 0 1.00 1.04 0 v/v ad8137w only: t min -t max 0.955 1.040 v/v v ocm input characteristics input voltage range 1.0 2.0 v ad8137w only: t min -t max 1.0 2.0 v input resistance 35 k? input offset voltage ?25 5.5 +2 5 mv ad8137w only: t min -t max ?25 +25 mv input voltage noise f = 100 khz to 5 mhz 18 nv/hz input bias current 0.3 0.7 a ad8137w only: t min -t max 0.7 a
ad8137 data sheet rev. e | page 8 of 32 parameter conditions min typ max unit cmrr v o, dm /v ocm , v ocm = 0.5 v 62 74 db ad8137w only: t min -t max 62 db power supply operating ran ge +2.7 6 v ad8137w only: t min - t max +2.7 6 v quiescent current 2.3 2.5 ma ad8137w only: t min -t max 2.5 ma quiescent current, disabled power - down = low 345 460 a ad8137w only: t min -t max 460 a psrr v s = 1 v 78 90 db ad8137w only: t min - t max 78 db pd pin threshold voltage v s? + 0.7 v s? + 1.5 v ad8137w only: t min -t max v s? + 0.7 v s? + 1.5 v input current power - down = high/low 8/65 10/70 a ad8137w only: t min -t max 10/75 a operating temperature range ?40 +125 c
data sheet ad8137 rev. e | page 9 of 32 absolute maximum rat ings table 4. parameter rating supply voltage 12 v v ocm v s+ to v s? power dissipation see figure 3 input common - mode voltage v s+ to v s? storage temperature range ? 65c to +125c operating temperature range ?40c to +125c lead temperature (soldering , 10 sec) 300c junction temperature 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stre ss rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst - case conditions, that is, ja is specified for the device soldered in a circuit board in still air. table 5 . thermal resistance package type ja jc unit 8- lead soic/2 - layer 157 56 c/w 8- lead soic/4 - layer 125 56 c/w 8- lead lfcsp/4 - layer 70 56 c/w maximum power dissip ation the maximum safe power dissipation in the ad8137 package is limited by the associated rise in junction temperature (t j ) on the di e. at approximately 150c, which is the glass transition temperature, the plastic changes its properties. even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric perf ormance of the ad8137 . exceeding a junction temperature of 175c for an extended period can result in changes in the silicon devices, potentially causing failure. the power dissipated in the package (p d ) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. the quiescent power is the voltage between the supply pins (v s ) times the quiescent current (i s ). the load current consists of differ ential and common - mode currents flowing to the load, as well as currents flowing through the external feedback networks and the internal common - mode feedback loop. the internal resistor tap used in the common - mode feedback loop places a 1 k? differential load on the output. rms output voltages should be considered when dealing with ac signals. airflow reduces ja . in addition , more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes reduces the ja . figure 3 shows the maximum safe power dissipation in the package vs. the ambient temperature for the 8 - lead soic (125c/w) and 8 - lead lfcsp ( ja = 70c/w) on a jedec standard 4 - layer board. ja values are approximations. ?40 ?20 ?10 ?30 0 10 20 30 40 50 60 70 80 90 100 110 120 3.0 maximum power dissipation (w) 1.0 1.5 0.5 2.0 2.5 0 ambient temperature ( c) soic-8 lfcsp 04771-0-022 figur e 3 . maximum power dissipation vs. ambient temperature for a 4 - layer board esd caution
ad8137 data sheet rev. e | page 10 of 32 pin configuration an d function descripti ons 04771-0-001 ?in 1 v ocm 2 v s+ 3 +out 4 +in 8 pd 7 v s? 6 ?out 5 ad8137 figure 4 . pin configuration table 6 . pin function descriptions pin o. nemonic description 1 ?in inverting input. 2 v ocm an internal feedback loop drives the output common - mode voltage to be equal to the voltage applied to the v ocm pin, provided the operation of the amplifier remains linear. 3 v s+ positive power supply voltage. 4 +out positive side of the differential output. 5 ?out negative side of the differential output. 6 v s? negative power supply voltage. 7 pd power down. 8 +in noninverting input. epad exposed p addle may be c onnect ed to either ground plane or po wer plane.
data sheet ad8137 rev. e | page 11 of 32 typical performance characteristics unless otherwise noted, differential gain = 1, r g = r f = r l, dm = 1 k?, v s = 5 v, t a = 25c, v ocm = 2.5v. refer to the basic test circuit in figure 60 for the definition of term s. r g = 1k? v o, dm = 0.1v p-p frequency (mhz) normalized closed-loop gain (db) 3 2 1 0 ?12 ?11 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0.1 1 10 100 1000 04771-0-002 g = 5 g = 10 g = 1 g = 2 figure 5 . small signal frequency response for various gains frequency (mhz) closed-loop gain (db) ?12 1 10 100 1000 04771-0-003 v s = 5 v s = +5 v s = +3 3 2 1 0 ?11 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 v o, dm = 0.1v p-p figure 6 . small signal frequency response for various power supplies frequency (mhz) closed-loop gain (db) 3 2 1 0 ?12 ?11 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 1 10 100 1000 04771-0-006 v o, dm = 0.1v p-p t = ?40c t = +125c t = +85c t = +25c figure 7 . small signal frequency re sponse at various temperatures frequency (mhz) normalized closed-loop gain (db) 3 2 1 0 ?12 ?11 ?10 ?9 ? 8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0.1 1 10 100 1000 04771-0-004 g = 10 g = 1 g = 2 g = 5 r g = 1k? v o, dm = 2.0v p-p figure 8 . large signal frequency response for various gains frequency (mhz) closed-loop gain (db) 4 3 2 1 0 ?11 ? 10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 1 10 100 1000 04771-0-005 v o, dm = 2.0v p-p v s = 5 v s = +5 v s = +3 figure 9 . large signal frequency response for various power supplies frequency (mhz) closed-loop gain (db) 4 3 2 1 ?11 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 10 100 1000 04771-0-007 t = +85c t = +125c t = ?40c t = +25c v o, dm = 2.0v p-p figure 10 . large signal frequency response at various temperatures
ad8137 data sheet rev. e | page 12 of 32 frequency (mhz) closed-loop gain (db) 3 2 1 0 ?1 ?3 ?4 ?2 ?5 ?6 ?7 ?8 ?10 ?11 ?9 ? 12 1 10 100 1000 04771-0-041 v o, dm = 0.1v p-p r l, dm = 2k? r l, dm = 1k? r l, dm = 500? figure 11 . small signal frequency response for various loads 1 10 100 1000 frequency (mhz) closed-loop gain (db) v o, dm = 0.1v p-p 3 2 1 0 ?12 ?11 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 04771-0-008 c f = 2pf c f = 1pf c f = 0pf figure 12 . small signal frequency response for various c f frequency (mhz) closed-loop gain (db) 2 1 0 ?1 ?2 ?4 ?5 ?3 ?6 ?7 ?8 ?9 ?11 ?12 ?10 ?13 1 10 100 1000 04771-0-042 v o, dm = 0.1v p-p v ocm = 1v v ocm = 4v v ocm = 2.5v figure 13 . small signal frequency response at various v ocm frequency (mhz) closed-loop gain (db) 3 2 1 0 ?1 ?3 ?4 ?2 ?5 ?6 ?7 ?8 ?10 ?11 ?9 ?12 1 10 100 1000 04771-0-043 v o, dm = 2v p-p r l, dm = 2k? r l, dm = 1k? r l, dm = 500? figure 14 . large signal frequency response for various loads 1 10 100 1000 frequency (mhz) closed-loop gain (db) v o, dm = 2.0v p-p 3 2 1 0 ?12 ?11 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 04771-0-009 c f = 2pf c f = 1pf c f = 0pf figure 15 . large signal frequency response for various c f frequency (mhz) closed-loop gain (db) 3 2 1 0 ?1 ?3 ?4 ?2 ?5 ?6 ?7 ?8 ?10 ?11 ?9 ?12 1 10 100 1000 04771-0-044 2v p-p 0.5v p-p 0.1v p-p 1v p-p f igure 16 . frequency response for various output amplitudes
data sheet ad8137 rev. e | page 13 of 32 frequency (mhz) closed-loop gain (db) 4 3 2 1 ?3 ?2 ?1 0 ?7 ?6 ?5 ?4 ?11 ?10 ?9 ?8 1 10 100 1000 04771-0-037 g = 1 v s = 5v v o, dm = 0.1v p-p r f = 500? r f = 2k? r f = 1k? figure 17 . small signal frequency response for various r f frequency (mhz) distortion (dbc) ?65 ?70 ?80 ?75 ?85 ?90 ?95 ?100 ?105 0.1 1 10 04771-0-045 v s = 5v v s = +5v v s = +3v g = 1 v o, dm = 2v p-p figure 18 . second harmonic distortion vs. frequency and supply voltage v o, dm (v p-p) distortion (dbc) ?50 ?60 ?65 ?70 ?55 ?75 ?80 ?85 ?90 ?95 ?100 0.25 1.25 2.25 3.25 4.25 5.25 7.25 8.25 6.25 9.25 04771-0-027 f c = 500khz second harmonic solid line third harmonic dashed line v s = +5v v s = +5v v s = +3v v s = +3v figure 19 . harmonic distortion vs. output amplitude and supply, f c = 500 khz frequency (mhz) closed-loop gain (db) 4 3 2 1 ?3 ?2 ?1 0 ?7 ?6 ?5 ?4 ?11 ?10 ?9 ?8 1 10 100 1000 04771-0-036 g = 1 v o, dm = 2v p-p r f = 500? r f = 2k? r f = 1k? figure 20 . large signal frequency response for various r f frequency (mhz) distortion (dbc) ?40 ?70 ?60 ?50 ?80 ?90 ? 100 ?110 0.1 1 10 04771-0-063 v s = 5v v s = +5v v s = +3v g = 1 v o, dm = 2v p-p figure 21 . third harmonic distortion vs. frequency and supply voltage v o, dm (v p-p) distortion (dbc) ?50 ?60 ?65 ?70 ?55 ?75 ?80 ?85 ?90 ?95 ?100 0.25 1.25 2.25 3.25 4.25 5.25 7.25 8.25 6.25 9.25 04771-0-026 v s = +5v v s = +5v v s = +3v v s = +3v f c = 2mhz s e c o n d h a r m o n i c s o l i d l i n e t h i r d h a r m o n i c d a s h e d l i n e figure 22 . harmonic distortion vs. output amplitude and supply, f c = 2 mhz
ad8137 data sheet rev. e | page 14 of 32 frequency (mhz) distortion (dbc) ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 0.1 1 10 04771-0-032 v o, dm = 2v p-p r l, dm = 200? r l, dm = 1k? r l, dm = 500? figure 23 . second harmonic distortion at various loads frequency (mhz) distortion (dbc) ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 0.1 1 10 04771-0-034 g = 2 g = 5 g = 1 v o, dm = 2v p-p r g = 1k? figure 24 . second harmonic distortion at various gains frequency (mhz) distortion (dbc) ? 40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 0.1 1 10 04771-0-030 v o, dm = 2v p-p g = 1 r f = 500? r f = 2k? r f = 1k ? figure 25 . second harmonic distortion at various r f frequency (mhz) distortion (dbc) ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 0.1 1 10 04771-0-033 v o, dm = 2v p-p r l, dm = 200? r l, dm = 1k? r l, dm = 500? figure 26 . third harmonic distortion at various loads frequency (mhz) distortion (dbc) ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 0.1 1 10 04771-0-035 v o, dm = 2v p-p r g = 1k? g = 5 g = 1 g = 2 figure 27 . third harmonic distortion at various gains frequency (mhz) distortion (dbc) ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 0.1 1 10 04771-0-031 v o, dm = 2v p-p g = 1 r f = 500? r f = 2k? r f = 1k? figure 28 . third harmonic distortion at various r f
data sheet ad8137 rev. e | page 15 of 32 v ocm (v) distortion (dbc) ?50 ?60 ?80 ?70 ?100 ?90 ?110 0.5 1.0 1.5 2.5 2.0 3.5 4.0 3.0 4.5 04771-0-028 f c = 500khz v o, dm = 2v p-p second harmonic solid line third harmonic dashed line figure 29 . harmonic distortion vs. v ocm , v s = 5 v frequency (hz) input voltage noise (nv/ hz) 100 10 1 10 100 1k 10k 100k 1m 10m 100m 04771-0-046 figure 30 . input voltage noise vs. frequency frequency (mhz) cmrr (db) 20 ?20 ?10 0 10 ?50 ?30 ?40 ?70 ?60 ?80 1 10 100 04771-0-013 v in, cm = 0.2v p-p input cmrr = ?v o, cm/ ?v in, cm figure 31 . cmrr vs. frequency v ocm (v) distortion (dbc) ?50 ?60 ?70 ?80 ?90 ?100 ?110 0.5 0.7 0.9 1.3 1.1 1.5 1.7 2.3 2.1 1.9 2.5 04771-0-029 f c = 500khz v o, dm = 2v p-p second harmonic solid line third harmonic dashed line figure 32 . harmonic distortion vs. v ocm , v s = 3 v frequency (hz) v ocm noise (nv/ hz) 1000 100 10 1 10 100 1k 10k 100k 1m 10m 100m 04771-0-047 figure 33 . v ocm voltage noise vs. frequenc y frequency (mhz) v ocm cmrr (db) ?10 ?30 ?20 ?50 ?40 ?70 ?60 ?80 1 10 100 04771-0-012 v o, cm = 0.2v p-p v ocm cmrr = ?v o, dm/ ?v ocm figure 34 . v ocm cmrr vs. frequency
ad8137 data sheet rev. e | page 16 of 32 time (ns) voltage (v) 8 2 4 6 0 ?4 ?2 ?6 ?8 04771-0-016 250ns/div input 2 output g = 2 figure 35 . overdrive recovery time (ns) v o, dm (mv) 100 50 25 75 0 ?25 ?50 ?75 ?100 04771-0-015 10ns/div v o, dm = 100mv p-p c f = 0pf c f = 1pf figure 36 . small signal transient response for various feedback capacitances time (ns) v o, dm (v) 100 50 25 75 0 ?50 ?25 ?75 ?100 04771-0-039 20ns/div r s = 111, c l = 5pf r s = 60.4, c l = 15pf figure 37 . small signal transient response for various capacitive loads 2.0 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.5 1.0 04771-0-040 amplitude (v) error (v) 1div = 0.02% c f = 0pf v o, dm = 3.5v p-p error = v o, dm - input t settle = 110ns 50ns/div v o, dm input time (ns) figure 38 . settling time (0.02%) 2v p-p 1v p-p time (ns) v o, dm (v) 1.5 1.0 ?0.5 0 0.5 ?1.0 ?1.5 04771-0-014 c f = 0pf c f = 1pf c f = 0pf c f = 1pf 20ns/div figure 39 . large signal transient response for various feedback capacitances time (ns) v o, dm (v) 1.5 0.5 1.0 0 ?0.5 ?1.0 ?1.5 04771-0-038 20ns/div r s = 111, c l = 5pf r s = 60.4, c l = 15pf figure 40 . large signal transient response for various capacitive loads
data sheet ad8137 rev. e | page 17 of 32 frequency (mhz) psrr (db) ?5 ?25 ?35 ?15 ?45 ?65 ?55 ?85 ?75 0.1 1 10 100 04771-0-011 psrr = ?v o, dm/ ?v s ?psrr +psrr figure 41 . psrr vs. frequency 1 10 100 1000 frequency (mhz) closed-loop gain (db) v o, dm = 0.1v p-p 1 0 ?1 ?2 ?14 ?13 ?12 ?11 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 04771-0-010 v s = +3 v s = +5 v s = 5 figure 42 . v ocm small signal frequency response for various supply voltages 700 ?700 ?600 ?500 ?400 ?300 ?200 ?100 0 100 200 300 400 500 600 200 1k 10k 04771-0-049 resistive load ( ?) single-ended output swing from rail (mv) v s+ ? v op v on ? v s? v s = +3v v s = +5v figure 43 . output saturation voltage vs. output load frequency (mhz) output impedance (?) 1000 100 10 1 0.1 0.01 0.01 100 10 1 0.1 04771-0-061 figure 44 . single - ended output impedance vs. frequency time (ns) v o, cm (v) 4.0 3.0 3.5 2.5 1.5 2.0 1.0 04771-0-050 20ns/div 2v p-p 1v p-p figure 45 . v ocm large signal transient response 320 350 ?330 ?325 ?320 ?315 ?310 ?305 ?300 345 340 335 330 325 ?40 ?20 0 20 40 60 80 100 120 04771-0-065 temperature (c) v op swing from rail (mv) v on swing from rail (mv) v on ? v s ? v s + ? v op figure 46 . output saturation voltage vs. temperature
ad8137 data sheet rev. e | page 18 of 32 ?0.3 0.3 ?15 10 5 0 5 10 15 0.2 0.1 0 ?0.1 ?0.2 ?40 ?20 0 20 40 60 80 100 120 04771-0-052 temperature ( c) v os, dm (mv) v os, cm (mv) v os, cm v os, dm figure 47 . offset voltage vs. temperature v acm (v) input bias current (a) 1.2 1.0 0.6 0.8 0.4 0.2 ?0.2 0 ?0.4 0.50 1.50 2.50 3.50 4.50 04771-0-059 figure 48 . input bias current vs. input common - mode voltage, v acm 0.10 0.40 ?3 ?2 ?1 0 1 2 3 0.35 0.30 0.25 0.20 0.15 ?40 ?20 0 20 40 60 80 100 120 04771-0-053 temperature (c) i bias (a) i os (na) i bias i os figure 49 . input bias and offset current vs. temperature temperature (c) supply current (ma) 2.60 2.55 2.45 2.40 2.50 2.35 2.30 ?40 0 20 ?20 40 80 100 60 120 04771-0-051 figure 50 . supply current vs. temperature v ocm (v) i v ocm (a) 70? 50 30 10 ?10 ?30 ?50 ?70 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 04771-0-056 figure 51 . v ocm bias current vs. v ocm input voltage ?0.5 ?0.1 ?0.2 ?0.3 ?0.4 ?40 ?20 0 20 40 60 80 100 120 04771-0-054 temperature (c) v ocm current (a) figure 52 . v ocm bias current vs. temperature
data sheet ad8137 rev. e | page 19 of 32 v ocm v o, cm 5 4 2 3 0 1 ?1 ?4 ?3 ?2 ?5 ?5 ?4 ?3 ?2 ?1 4 3 2 1 0 5 04771-0-060 v s = +3v v s = +5v v s = 5v figure 53 . v o, cm vs. v ocm input voltage pd voltage (v) pd current (a) 40? 20 0 ?20 ?40 ?60 ?80 ?100 ?120 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 04771-0-057 figure 54 . pd current vs. pd voltage pd voltage (v) supply current (ma) 3 2 1 0 ?1 ?2 ?3 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 04771-0-058 i s + i s ? figure 55 . supply current vs. pd voltage pd ?2.0v ?0.5v v o, dm 2s/div v s = 2.5v g = 1 (r f = r g = 1k?) r l, dm = 1k? input = 1vp-p @ 1mhz time (s) supply current (ma) 1.5 1.0 0.5 ?0.5 0 ?1.0 ?1.5 04771-0-066 figure 56 . power - down transient response time (ns) supply current (ma) 3.6 3.2 2.8 2.0 2.4 0.8 1.2 1.6 0.4 0 04771-0-024 100ns/div pd (0.8v to 1.5v) figure 57 . power - down turn - on time time (ns) supply current (ma) 3.4 3.0 2.6 2.2 1.8 1.4 1.0 0.6 0.2 04771-0-025 40ns/div pd (1.5v to 0.8v) figure 58 . power - down turn - o ff time
ad8137 data sheet rev. e | page 20 of 32 04771-071 0 5 10 15 20 25 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 supp l y current (ma) power-down vo lt age (v) v s = 5v v ocm = 0v g = +1 figure 59 . supply current vs. power - down voltage
data sheet ad8137 rev. e | page 21 of 32 test circuits ad8137 + ? 52.3? 52.3? r l, dm 1k? v o, dm + ? v ocm r f c f r f v test test signal source 50? 50? 04771-0-023 r g = 1k? r g = 1k? c f midsupply figure 60 . basic test circuit ad8137 + ? 52.3? 52.3? r l, dm v o, dm + ? r f = 1k? r f = 1k? r s r s v test test signal source 50? 50? 04771-0-062 c l, dm r g = 1k? r g = 1k? v ocm midsupply figure 61 . capacitive load test circuit, g = 1
ad8137 data sheet rev. e | page 22 of 32 theory of ope ration the ad8137 is a low power, low cost, fully differential voltage feedback amplifier that features a rail - to - rail output stage, common - mode circuitry with an internally derived common - mode reference volta ge, and bias shutdown circuitry. the amplifier uses two feedback loops to separately control differential and common - mode feedback. the differential gain is set with external resistors as in a traditional amplifier , and the output common - mode voltage is se t by an internal feedback loop, controlled by an external v ocm input. this architecture makes it easy to set arbitrarily the output common - mode voltage level without affecting the differential gain of the amplifier. ?out +in a cm v ocm c c c c cp +out ?in cn 04771-0-017 figure 62 . bl ock diagram from figure 62 , the input transconductance stage is an h - bridge whose output current is mirrored to high impedance nodes cp and cn. the output section is traditional h - bridge driven circuitry with common emitter de vices driving nodes +out and ?out. the 3 db point of the amplifier is defined as c m c g bw = 2 where: g m is the transconductance of the input stage . c c is the total capacitance on node cp/cn (capacitances cp and cn are well matched). for the ad8137 , the input stage g m is ~1 ma/v and the capacitance c c is 3.5 pf, setting the crossover frequency of the amplifier at 41 mhz. this frequency generally establishes an amplifiers unity gain bandwidth, but wi th the ad8137 , the closed - loop bandwidth depends upon the feedback resistor value as well (see figure 17 ). the open - loop gain and phase simulations are shown in figure 63. frequency (mhz) 100 80 ?60 ?40 ?20 0 20 40 60 ?120 ?100 ?80 ?200 ?180 ?160 ?140 0.0001 0.01 0.001 0.1 1 10 100 04771-0-021 open-loop gain (db) phase (degrees) figure 63 . open - loop gain and phase in figure 62 , the common - mode feedback amplifier a cm samples the output common - mode voltage, and by negative feedback forces the output common - mode voltage to be equal to the voltage applied to the v ocm input. in other words, the feedback loop servos the output common - mode voltage to the voltage applied to the v ocm input. an internal bias generator sets the v ocm level to approximately midsupply; therefore, the output common - mode voltage is set to approximately midsupply when the v ocm input is left floating. the source resistance of the internal bias generator is large and can be overridden easily by an external voltage supplied by a source with a relatively small output resistance. the v ocm input can be driven to within approximately 1 v of the supply rails while maintaining linear operation in the common - mode feedback loop. the common - mode feedback loop inside the ad8137 produces outputs that are highly balanced over a wide frequency range without the requirement of tightly matched external components, because it forces the signal component of the output common - mode voltage to be zeroed. the result is nearly perfectly balanced differential outputs of identical amplitude and exactly 180 apart in ph ase.
data sheet ad8137 rev. e | page 23 of 32 applications information analyzing a typical application with matched r f and r g networks typical connection and definition of terms figure 64 shows a typical connection for the ad8137 , using matched external r f /r g networks. the differential input terminals of the ad8137 , v ap and v a n , are used as summing junctions. an external reference voltage applied to the v ocm terminal sets the output common - mode voltage. the two output terminals, v op and v on , move in opposite directions in a balanced fashion in response to an input signal. 04771-0-055 + ? v ap v an v on v op ? + v o, dm r l, dm ad8137 c f r f r g r g c f r f v ip v ocm v in fi gure 64 . typical connection the differential output voltage is defined as v o, dm = v op ? v on (1) common - mode voltage is the average of two voltages. the output common - mode voltage is defined as 2 , on op cm o v v v + = (2) output ba lance output balance is a measure of how well v op and v on are matched in amplitude and how precisely they are 180 out of phase with each other. it is the internal common - mode feedback loop that forces the signal component of the output common - mode toward zero, resulting in the near perfectly balanced differential outputs of identical amplitude and are exactly 180 out of phase. the output balance performance does not require tightly matched external components, nor does it require that the feedback factors of each loop be equal to each other. low frequency output balance is ultimately limited by the mismatch of an on - chip voltage divider. output balance is measured by placing a well - matched resistor divider across the differential voltage outputs and compa ring the signal at the dividers midpoint with the magnitude of the differential output. by this definition, output balance is equal to the magnitude of the change in output common - mode voltage divided by the magnitude of the change in output differential mode voltage: dm o cm o v v balance output , , ? ? = (3) the differ ential negative feedback drives the voltages at the summing junctions v an and v ap to be essentially equal to each other. v an = v ap (4) the common - mode feedback loop drives the output common - mode voltage, s ampled at the midpoint of the two internal common - mode tap resistors in figure 62 , to equal the voltage set at the v ocm terminal. this ensures that 2 , dm o ocm op v v v + = (5) and 2 , dm o ocm on v v v ? = (6) estimating noise, ga in, and bandwith wit h matched feedback net works estimating output noise voltage and bandwidth the total output noise is the root - sum - squared total of several statistically independent sources. because the sources are statistically independent, the contribu tions of each must be in dividually included in the root - sum - square calculation. table 7 lists recommended resistor values and estimates of bandwidth and output differential voltage noise for various closed - loop gains. for most applications, 1% resistors are sufficient. table 7 . recommended values of gain - setting resistors and voltage gain for various closed - loop gains gain r g (?) r f (?) 3 db bandwidth (mhz) total output noise (nv/hz) 1 1 k 1 k 72 18.6 2 1 k 2 k 40 28.9 5 1 k 5 k 12 60.1 10 1 k 10 k 6 112.0
ad8137 data sheet rev. e | page 24 of 32 the differential output voltage noise contains contributions from the ad8137 s input voltage noise and input current noise as well as those from the external feedback networks. the contribution from the input voltage noise spectral density is computed as ? ? ? ? ? ? + = g f n r r v vo_n 1 1 , or equivalently, v n / (7) where v n is defined as the input - referred differential voltage noise. this equation is the same as that of traditional op amps. the contribution from the input current noise of each input is computed as ( ) f n r i vo_n = 2 (8) where i n is defined as the input noise current of one input. each input needs to be treated separately because the two input currents are statistically independent processes. the contribution from each r g is computed as ? ? ? ? ? ? = g f g r r tr vo_n k 4 3 (9) this result can be intuitive ly viewed as the thermal noise of each r g multiplied by the magnitude of the differential gain. the contribution from each r f is computed as f tr vo_n k 4 4 = (10) voltage gain the behavior of the node voltages of the single - ended - to - differential outp ut topology can be deduced from the signal definitions and figure 64 . referring to figure 64 , c f = 0 and setting v in = 0 , one can writ e : f on ap g ap ip r v v r v v ? = ? (11) ? ? ? ? ? ? + = = g f g op ap an r r r v v v (12) solv ing the previous two equations and setting v ip to v i gives the gain relationship for v o, dm /v i . i g f dm o, on op v r r v v v = = ? (13) an inverting configuration with the same gain magnitude can be implemented by simply applying the input signal to v in and setting v i p = 0. for a balanced differential input, the gain from v in, dm to v o, dm is also equal to r f /r g , where v in, dm = v ip ? v in . feedback factor notation when working with differential drivers, it is convenient to introduce the feedback factor , which is def ined as g f g r r r + (14) this notation is consistent with conventional feedback analysis and is very useful, particularly when the two feedback loops are not matched. input common - mode voltage the linear range of the v an and v ap terminals extend s to within approximately 1 v of either supply rail. because v an and v ap are essentially equal to each other, they are both equal to the amplifiers input common - mode voltage. their range is indicated in the specifications tables as input common - mode range . the voltage at v an and v ap for the connection diagram in figure 64 can be expressed as v an = v ap = v acm = ( ) ? ? ? ? ? ? ? ? + + ? ? ? ? ? ? ? ? + + ocm g f g in ip g f f v r r r v v r r r 2 (15) where v acm is the common - mode voltage present at the amplifier input terminals. using the notation, equ ation (15) can be written as v acm = v ocm + (1 ? ) v icm (16) or equivalently, v acm = v icm + ( v ocm ? v icm ) (17) where v icm is the common - mode voltage of the input signal, that is 2 in ip icm v v v + for proper operation, the voltages at v a n and v ap must stay within their respective linear ranges. calculating input impedance the input impedance of the circuit in figure 64 depends on whether the amplifier is being driven by a single - ended or a differential signal source. for balanced differential input signals, the differential input impedance (r in, dm ) is simply r in, dm = 2 r g (18) for a single - ended signal (for example, when v in is grounded and the input signal drives v ip ), the input impedance becomes ) ( 2 1 f g f g in r r r r r + ? = (19)
data sheet ad8137 rev. e | page 25 of 32 04771-0-018 gnd v ref v refa adr525a 2.5v shunt reference ad7450a v in + v in ? vdd ad8137 + ? 8 v refb 2.5v 2 1 6 3 4 5 v ocm 1k? 1k? 1k? 2.5k? 1k? 5v 50? 50? v in 1.0nf 1.0nf 0.1f 0.1f +1.88v +1.25v v acm with v refb = 0 +0.63v +2.5v gnd ?2.5v figure 65 . ad8137 driving ad7450a, 12 - bit ad c the input impedance of a conventional inverting op amp configuration is simply r g ; however, it is higher in equation 19 because a fraction of the differential ou tput voltage appears at the summing junctions, v an and v ap . this voltage partially bootstraps the voltage across the input resistor r g , leading to the increased input resistance. input common - mode swing considerations in some single - ended - to - differential a pplications , when using a single - supply voltage, attention must be paid to the swing of the input common - mode voltage, v acm . consider the case in figure 65 , where v in is 5 v p - p swinging about a baseline at ground and v refb is connected to ground. the input signal to the ad8137 is originating from a source with a very low output resistance. the circuit has a differential gain of 1.0 and = 0.5. v icm has an amplitude of 2.5 v p - p and is swinging about ground. using the results in equation 16, the common - mode voltage at the inputs of the ad8137 , v a cm , is a 1.25 v p - p signal swinging about a baseline of 1.25 v. the maximum negative excursion of v acm in this case is 0.63 v, which exceeds the lower input common - mode voltage limit. one way to avoid the input common - mode swing limitation is to bias v in a nd v ref at midsupply. in this case, v in is 5 v p - p swinging about a baseline at 2.5 v, and v ref is connected to a low - z 2.5 v source. v icm now has an amplitude of 2.5 v p - p and is swinging about 2.5 v. using the results in equation 17, v acm is calculated t o be equal to v icm because v ocm = v icm . therefore, v icm swings from 1.25 v to 3.75 v, which is well within the input common - mode voltage limits of the ad8137 . another benefit seen by this example is that becaus e v ocm = v acm = v icm , no wasted common - mode current flows. figure 66 illustrates a way to provide the low - z bias voltage. for situations that do not require a precise reference, a simple voltage divider suffice s to develop the input voltage to the buffer. 04771-0-019 v in 0v to 5v ad8137 + ? 8 2 1 6 3 4 5 v ocm 1k? 1k? 5v 1k? 1k? 10k? 0.1f 0.1f 0.1f 10f + ad8031 + ? 0.1f 5v adr525a 2.5v shunt reference to ad7450a v ref figure 66 . low - z bias source another way to avoid the input common - mode swing limitation is to use dual power supplies on the ad8137 . in this case, the bi asing circuitry is not required. bandwidth vs. closed - loop gain the 3 db bandwidth of the ad8137 decrease s proportionally to increasing closed - loop gain in the same way as a traditional voltage feedback operat ional amplifier. for closed - loop gains greater than 4, the bandwidth obtained for a specific gain can be estimated as ) mhz 72 ( , 3 + = ? (20) or equivalently, (72 mhz). this estimate assumes a minimum 90 phase margin for the amplifier loop, a condit ion approached for gains greater than 4 . lower gains show more bandwidth than predicted by the equation due to the peaking produced by the lower phase margin.
ad8137 data sheet rev. e | page 26 of 32 estimating dc errors primary differential output offset errors in the ad8137 are due to three major components: the input offset voltage, the offset between the v an and v ap input currents interacting with the feedback network resistances, and the offset produced by the dc voltage difference between the in put and output common - mode voltages in conjunction with matching errors in the feedback network. the first output error component is calculated as ? ? ? ? ? ? + = g g f io r r r v vo_e 1 , or equivalently as v io / (21) where v io is the input offset voltage. the second erro r is calculated as ( ) f io g f f g g g f io r i r r r r r r r i vo_e = ? ? ? ? ? ? + ? ? ? ? ? ? + = 2 (22) where i io is defined as the offset between the two input bias currents. the third error voltage is calculated as vo_e3 = enr ( v icm ? v ocm ) (23) where enr is the fractional mismatch between the two feedback resistors. the total differential offset error is the sum of these three error sources. additional impact of mismatches in the feedback networks the internal common - mode feedback network still force s the output voltages to remain balanced, even when the r f /r g feed - back networks are mismatched. the mismatch , however, cause s a gain error proportional to the feedback network mismatch. ratio - matching errors in the external resistors degrade the ability to reject common - mode signals at the v an and v in input te rminals, similar to a four resistor , difference amplifier made from a conventional op amp. ratio - matching errors also produce a differential output component that is equal to the v ocm input voltage times the difference between the feedback factors (s). in most applications using 1% resistors, this component amounts to a differential dc offset at the output that is small enough to be ignored. driving a capacitive load a purely capacitive load react s with the bondwire and pin inductance of the ad8137 , resulting in high frequency ringing in the transient response and loss of phase margin. one way to minimize this effect is to place a small resistor in series with each output to buffer the load capacitance. the re sistor and load capacitance form s a first - order, low - pass filter ; therefore, the resistor value should be as small as possible. in some cases, the adcs require small series resistors to be added on their inputs. figure 37 and figure 40 illustrate transient response vs. capacitive load and were generated using series resistors in each output and a differential capacitive load. layout considerations standard high speed pcb layout practices should be ad hered to when designing with the ad8137 . a solid ground plane is recommended and good wideband power supply decoupling networks should be placed as close as possible to the supply pins. to minimize stray capac itance at the summing nodes, the copper in all layers under all traces and pads that connect to the summing nodes should be removed. small amounts of stray summing - node capacitance cause peaking in the frequency response, and large amounts can cause inst ability. if some stray summing - node capacitance is unavoidable, its effects can be compensated for by placing small capacitors across the feedback resistors. terminating a single - ended input controlled impedance interconnections are used in most high speed signal applications, and they require at least one line termination. in analog applications, a matched resistive termination is generally placed at the load end of the line. this section deals with how to properly terminate a single - ended input to the ad8137 . the input resistance presented by the ad8137 input circuitry is seen in parallel with the termination resistor, and its loading effect must be taken into accou nt. the thevenin equivalent circuit of the driver, its source resistance, and the termination resistance must all be included in the calculation as well. an exact solution to the problem requires solution of several simultaneous algebraic equations and is beyond the scope of this data sheet. an iterative solution is also possible and is easier , especially considering the fact that standard resistor values are generally used.
data sheet ad8137 rev. e | page 27 of 32 figure 67 shows the ad8137 in a unity - gain configuration, and with the following discussion, provides a good example of how to provide a proper termination in a 50 ? environment. ad8137 + ? 8 2 1 6 3 4 0v 2v p-p r t 52.3? 5 + ? v ocm 1k? 1.02k? 1k? 1k? 0.1f 0.1f +5v ?5v v in signal source 50? 04771-0-020 figure 67 . ad8137 with terminated input the 52.3 ? termination resistor, r t , in parallel with the 1 k ? input resistance of the ad8137 circuit, yields an overall input r esistance of 50 ? that is seen by the signal source. t o have matched feedback loops, each loop must have the same r g i f it has the same r f . in the input (upper) loop, r g is equal to the 1 k ? resistor in series with the (+) input plus the para llel combination of r t and the source resistance of 50 ? . in the upper loop, r g is therefore equal to 1.03 k ? . the closest standard value is 1.02 k ? and is used for r g in the lower loop. things become more complicated when it comes to determining the feedback resistor values. the amplitude of the signal source generator v in is two times the amplitude of its output signal when terminat ed in 50 ? . therefore, a 2 v p - p terminated amplitude is produced by a 4 v p - p amplitude from v s . the thevenin equivalent circuit of the signal source and r t must be used when calculating the closed - loop gain because r g in the upper loop is split between t he 1 k? resistor and the thevenin resistance looking back toward the source. the thevenin voltage of the signal source is greater than the signal source output voltage when terminated in 50 ? because r t must always be greater than 50 ? . in this case, r t is 52.3 ? and the thevenin voltage and resistance are 2.04 v p - p and 25.6 ?, respectively. now the upper input branch can be viewed as a 2.04 v p - p source in series with 1.03 k?. because this is to be a unity - gain application, a 2 v p - p differential output i s required, and r f must therefore be 1.03 k? (2/2.04) = 1.01 k? 1 k ? . this example shows that when r f and r g are large compared to r t , the gain reduction p roduced by the increase in r g is essentially cancelled by the increase in the thevenin voltage ca used by r t being greater than the output resistance of the signal source. in general, as r f and r g become smaller in terminated applications, r f needs to be increased to compensate for the increase in r g . when generating the typical performance characteris tics data, the measurements were calibrated to take the effects of the terminations on closed - loop gain into account. power - down the ad8137 features a pd pin that can be used to minimize the quiescent current consumed when the device is not being used. pd is asserted by applying a low logic level to pin 7. the threshold between high and low logic levels is nominally 1.1 v above the negative supply rail. see table 1 to table 3 for the threshold limits. the ad8137 pd pin features an internal pull - up network that enables the amplifier for nor mal operation . the ad8137 pd pin can be left floating ( that is, no external connection is required ) and do es not require an external pull - up resistor to ensure normal on operation (s ee figure 68) . do not connect the pd pin directly to v s+ in 5 v applications . this can cause the amplifier to draw excessive supply current (see figure 59) and may induce oscillations a nd/or stability issues. 50k? 5k? 150k? ref a pd ?v s +v s +v s q1 q2 04771-072 figure 68 . pd pin c ircuit driving an adc with greater than 12 - bit performance because the ad8137 is suitable for 12 - bit systems, it is d esirable to measure the performance of the amplifier in a system with greater than 12 - bit linearity. in particular, the effective number of bits ( enob ) is most interesting. the ad7687 , 16 - bit, 250 ksps adc perf ormance makes it an ideal candidate for showcasing the 12 - bit performance of the ad8137 . for this application, the ad8137 is set in a gain of 2 and driven single - e nded through a 20 khz band - pass filter, while the output is taken differentially to the input of the ad7687 (see figure 69 ). this circuit has mismatched r g impedances and, therefore , has a dc offset at the differential output. it is included as a test circuit to illustrate the performance of the ad8137 . actual application circuits should have matched feedback networks. for an ad7687 input range up to ?1.82 dbfs, the ad8137 power supply is a single 5 v applied to v s+ with v s ? tied to ground. to increase the ad7687 input range to ?0.45 dbfs, the ad8137 supplies are increased to +6 v and ?1 v. in both cases, the v ocm pin is biased with 2.5 v and the pd pin is left floating. all voltage supplies are decoupled with 0.1 f capacitors . figure 70 and figure 71 show the performance of the ?1.82 dbfs setup and the ?0.45 dbfs setup, respectively.
ad8137 data sheet rev. e | page 28 of 32 ad8137 + ? 1nf 1nf v ocm v s ? v s + v+ 1.0k? 1.0k? 20khz 33? 33? 04771-0-067 499? 499? +2.5 ad7687 gnd v dd v in gnd bpf figure 69 . ad8137 driving ad7687, 16 - bit 250 ksps adc frequency (khz) amplitude (db of full scale) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 ?160 ?170 0 40 20 60 120 100 80 140 04771-0-068 thd = ?93.63dbc snr = 91.10db sinad = 89.74db enob = 14.6 figure 70 . ad8137 performance on single 5 v supply, ?1.82 dbfs frequency (khz) amplitude (db of full scale) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 ?160 0 40 20 60 120 100 80 140 04771-0-069 thd = ?91.75dbc snr = 91.35db sinad = 88.75db enob = 14.4 figure 71 . ad8137 performance on +6 v, ?1 v supplies, ?0.45 dbfs
data sheet ad8137 rev. e | page 29 of 32 outline dimensions controlling dimensions are in millimeters; inch dimensions (in p arentheses) are rounded- off millimeter equiv alents for reference onl y and are not appropria te for use in design. compliant t o jedec st andar ds ms-012-aa 012407-a 0.25 (0.0098) 0.17 (0.006 7) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) sea ting plane 0.25 (0.0098) 0.10 (0.0040) 4 1 8 5 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 figure 72 . 8 - lead stan dard small outline package [soic_n] narrow body (r - 8) dimensions shown in millimeters and (inches) t op view 8 1 5 4 0.30 0.25 0.20 b o t t o m v i e w pin 1 index area sea ting plane 0.80 0.75 0.70 1.55 1.45 1.35 1.84 1.74 1.64 0.203 ref 0.05 max 0.02 nom 0.50 bsc e x p o s e d p a d 3.10 3.00 sq 2.90 for proper connection of the exposed pad, refer to the pin configuration and function descripti ons section of this data sheet. coplanarity 0.08 0.50 0.40 0.30 compliant t o jedec standards mo-229-weed 12-07-2010-a pin 1 indica t or (r 0.15) figure 73 . 8 - lead lead f rame chip scale package [lfcsp_ w d] 3 mm 3 mm body, very very thin, dual lead (cp - 8 - 13) dimensions shown in millimeters
ad8137 data sheet rev. e | page 30 of 32 ordering guide mode l 1 , 2 temperature range package description package option branding ad8137yr ?40c to +125c 8- lead standard small outline package (soic_n) r -8 ad8137yr - reel7 ?40c to +125c 8- lead standard small outline package (soic_n) r -8 ad8137yrz ?40c to +125c 8- lead standard small outline package (soic_n) r -8 ad8137yrz - reel ?40 c to +125c 8- lead standard small outline package (soic_n) r -8 ad8137yrz - reel7 ?40c to +125c 8- lead standard small outline package (soic_n) r -8 ad8137ycpz - r2 C 40c to +125c 8 - lead lead frame chip scale package (lfcsp_ w d) cp - 8 - 13 hfb# ad8137ycpz - reel C40 c to +125c 8- lead lead frame chip scale package (lfcsp_ w d) cp -8-13 hfb# ad8137ycpz - reel7 C 40c to +125c 8- lead lead frame chip scale package (lfcsp_ w d) cp -8-13 hfb# ad8137w y cpz - r7 C 40c to +125c 8- lead lead frame chip scale package (lfcsp_ w d) cp -8-13 h2 g ad8137ycp - ebz lfcsp evaluation board ad8137yr - ebz soic evaluation board 1 z = rohs compliant part; # de notes that rohs part may be top or bottom marked. 2 w = qualified for automotive applications . automotive products the ad8137w models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the specifications section of this data sheet carefully. only the automotive grade products shown are available for use in automotive applications. contact your local analog devices account representative for specific product ordering information a nd to obtain the specific automotive reliability reports for these models.
data sheet ad8137 rev. e | page 31 of 32 notes
ad8137 data sheet rev. e | page 32 of 32 notes ? 2004 C 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d04771 - 0 - 7/12(e)

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